TASER: Topics in hArdware SEcurity and RISC-V

September 13, 2021, virtual

About

Videos of the talks are now available on YouTube

The open nature of, and both eco-system and community associated with RISC-V has arguably led to a "golden period" of research and innovation within the field of computer architecture. This, in turn, has positively impacted the associated field of hardware security, where significant existing challenges remain and new challenges continue to emerge. For example, use of RISC-V in this context offers opportunities (for academic and industrial research and development) which stem from the extensible, configurable nature of the ISA and many associated implementations, plus transparency afforded by access to HDL for many such implementations.
The TASER workshop broadly aims to establish hardware security using RISC-V as a topic of interest for the CHES community. This inaugural edition will feature around six invited talks (each of around 20 minutes), on topics spanning the field, i.e. both in the core and at the periphery of CHES:

• processor and co-processor RISC-V implementations
• RISC-V optimised software implementation
• security-oriented instruction set extensions
• security-oriented verification
• Trusted Execution Environments (TEEs) and related technologies
• memory protection and control-flow integrity technologies
• side-channel attacks and countermeasures

Program

All times in CEST.

• 17:00 - 17:05 Opening, Dan Page, University of Bristol


• 17:05 - 17:25 An overview of security topics within RISC-V, Helena Handschuh, Rambus
• 17:25 - 17:30 Q&A


• 17:30 - 17:50 RISC-V cryptography extensions: current status and future plans, Ben Marshall, University of Bristol and PQShield
• 17:50 - 17:55 Q&A


• 17:55 - 18:15 Coco: Co-Design and Co-Verification of Masked Software Implementations on CPUs, Barbara Gigerl, IAIK - TU Graz
• 18:15 - 18:20 Q&A


• 18:20 - 18:40 Can we solve timing side-channels in the CPU?, Ronan Lashermes, INRIA
• 18:40 - 18:45 Q&A


• 18:45 - 19:05 Current status of RISC-V security mechanisms, Nick Kossifidis, FORTH
• 19:05 - 19:10 Q&A


• 19:10 - 19:30 CHERI and CHERI-RISC-V, Simon Moore, University of Cambridge
• 19:30 - 19:35 Q&A


• 19:35 - 19:40 Closing Remarks, Dan Page, University of Bristol

Registration

TASER is an affiliated event with CHES 2021. Please register with the conference to attend the workshop.

Organizers

• Dan Page (University of Bristol)
• Helena Handschuh (Rambus)
• Benedikt Gierlichs (KU Leuven)
• Richard Newell (Microchip)

Last update: 2021-09-08