TASER: Topics in hArdware SEcurity and RISC-V

September 13, 2021, virtual

RISC-V logo


Videos of the talks are now available on YouTube

The open nature of, and both eco-system and community associated with RISC-V has arguably led to a "golden period" of research and innovation within the field of computer architecture. This, in turn, has positively impacted the associated field of hardware security, where significant existing challenges remain and new challenges continue to emerge. For example, use of RISC-V in this context offers opportunities (for academic and industrial research and development) which stem from the extensible, configurable nature of the ISA and many associated implementations, plus transparency afforded by access to HDL for many such implementations.
The TASER workshop broadly aims to establish hardware security using RISC-V as a topic of interest for the CHES community. This inaugural edition will feature around six invited talks (each of around 20 minutes), on topics spanning the field, i.e. both in the core and at the periphery of CHES:


All times in CEST.


TASER is an affiliated event with CHES 2021. Please register with the conference to attend the workshop.


Last update: 2021-09-08