Hardware for privacy engineering
Ensuring that systems are privacy-preserving requires careful design at all layers. Many times it is believed that cryptography is the key to the problem. In practice, this typically involves more than designing, implementing, and composing privacy-preserving cryptographic primitives. In this talk, we will explore different techniques that are used by privacy engineers to build end-to-end privacy-preserving systems, what hurdles engineers find when deploying privacy technologies, and how better hardware support could improve the situation fostering the adoption of privacy-preserving solutions at large scale.
Carmela Troncoso is an Assistant Professor at EPFL (Switzerland) where she heads the SPRING Lab. Her research covers a wide range of topics that are essential to enable the development of technology that can be used to build socially responsible systems. Most of her work focuses on analyzing, building, and deploying secure and privacy-preserving systems. Her work on privacy engineering received the CNIL-INRIA Privacy Protection Award in 2017, and she has been named 40 under 40 in technology by Fortune in 2020 for her work on contact tracing apps.
From CHERI to Arm Morello: Architectural Support for Memory Protection and Software Compartmentalization
Dr Robert N. M. Watson is Reader in Systems, Security, and Architecture at the University of Cambridge Department of Computer Science and Technology. Since 2010, he has led the DARPA-supported team developing a new processor architectural protection model known as CHERI (Capability Hardware Enhanced RISC Instructions). The CHERI project has been full stack research, iteratively modifying the Instruction-Set Architecture (ISA) and exploring the implications for microarchitecture (prototyped on FPGA), the operating system, compiler, and applications, as well as using formal modelling and proof on the ISA itself. CHERI enables fine-grained C and C++ memory protection as well as scalable software compartmentalization. In 2019, Arm announced Morello, an application of the CHERI protection model to its ARMv8-A ISA and Neoverse N1 microarchitecture, with a first experimental ARM processor, System-on-Chip (SoC), and board available from 2022. Morello is the centrepiece of the £187M UKRI Digital Security by Design (DSbD) research programme across UK academia and industry including Arm, Linaro, Google, and Microsoft. Having recently gone to tape-out, the first Morello CPUs are due back from fabrication in late 2021. This talk will explore the approach, history, and next directions for CHERI.