CHES 2026

Time:

Sunday, October 11, 2026

Location:

TBA

Speaker:

• Abdullah Talayhan, Bilkent University, Türkiye

Abstract:

GPU acceleration has become essential for performance-critical cryptographic workloads. Polyno- mial arithmetic (via the Number Theoretic Transform) and multi-scalar multiplication are naturally suited to GPU parallelism and dominate the cost of fully homomorphic encryption schemes and zero-knowledge proof systems. GPU-accelerated libraries are now appearing for post-quantum cryptography as well. Yet the overwhelming majority of GPU implementations of these primitives target a single vendor’s proprietary platform, excluding most of the important deployment settings such as client-side proving in browsers, mobile devices, and heterogeneous cloud environments.reached real-world deployment and market-ready levels.

This half-day tutorial introduces the CHES community to portable GPU programming for crypto- graphic workloads. We begin by identifying the small set of core operations: modular arithmetic over fields of widely varying sizes, NTT, and hashing. Although these operations share common structure (heavy in finite field arithmetic), their implementation requirements diverge considerably. We examine how these differences interact with GPU hardware constraints.

We then survey the current landscape of cross-platform GPU compute frameworks, including Vulkan-based wrappers, WebGPU, and higher-level domain-specific languages. Lastly, we dis- cuss open engineering challenges of building portable cryptographic compute libraries for the community.

The tutorial will include a hands-on component in which participants implement GPU kernels targeting more than one GPU backend. All the necessary material will be distributed to the participants as a portable development environment in advance. The goal is to make the attendees leave with practical experience in portable GPU programming for cryptography and a summary of the open problems in this space to engage in further discussion.

Requirements/Prerequisites:

Cryptography engineers and researchers working on implementations of post-quantum schemes, zero-knowledge proof systems, or fully homomorphic encryption, as well as anyone interested in GPU acceleration of cryptographic primitives. We estimate 50–60 attendees. The tutorial is accessible to anyone comfortable with finite field arithmetic and common algorithms like NTT; no prior GPU programming experience is assumed.

Participants are encouraged to bring laptops. A pre-configured environment with the necessary toolchains and starter code will be distributed before the tutorial to minimize setup time. No specialized hardware is required. Attendees without laptops will be able to follow along via the projector

Time:

Sunday, October 11, 2026

Location:

TBA

Speakers:

• Dr. Mahshid Delavar, Lecturer (Assistant Professor) in Cybersecurity, University of Sheffield, UK
• Dr. Meltem Kurt Pehlivanoğlu, Lecturer (Associate Professor), Computer Engineering Department, Kocaeli University, Turkey
• Oğuz Narlı, Senior Embedded Software Engineer, CTech Information Technologies, Turkey

Abstract:

Physical Unclonable Functions (PUFs) are a familiar topic in the CHES community, with established applications in authentication, key generation, and anti-counterfeiting. More recently, the notion of a Quantum Physical Unclonable Function (qPUF) has begun to emerge, but the term is not yet used in a single consistent way. Different works and communities use it to describe different types of primitives based on different physical assumptions, implementation strategies, and security goals. As a result, qPUFs currently form a promising but fragmented research area. This tutorial aims to equip the CHES community with a shared vocabulary, a clear taxonomy, and a concrete research map for qPUFs, so that researchers can engage critically and productively with this emerging area.

Rather than presenting qPUFs as a single fixed primitive, the tutorial will organize the area into a coherent taxonomy. It will first briefly revisit classical PUFs and explain why their limitations motivate interest in quantum-enhanced unclonability. It will then identify and compare the main ways the term qPUF is used, including approaches based on quantum challenge-response interactions, quantum readout of complex physical structures, and hardware realizations based on specifically quantum physical effects and devices, such as tunneling-based implementations and quantum-dot systems. For each category, the tutorial will discuss the underlying assumptions, intended security benefits, implementation strategies, and practical limitations.

A central focus of the tutorial will be comparison. The session will examine what is genuinely “quantum” in each qPUF category, what advantages may be gained over classical PUFs, and what new constraints or attack surfaces may arise. It will compare categories in terms of unclonability assumptions, verifier requirements, robustness, scalability, practicality, and suitability for applications such as authentication, attestation, and anti-counterfeiting. It will also identify the main open research questions in the area, including formal definitions, evaluation and benchmarking, appropriate threat models, reliability and repeatability, and realistic paths toward hardware-security deployment.

The tutorial will include two short interactive activities: a classification exercise in which attendees map example proposals into qPUF categories, and a guided discussion on which open problems are most important for the CHES community to address next.

Learning outcomes. By the end of the tutorial, attendees will be able to:

1. Distinguish between multiple meanings of qPUF in the literature;
2. Compare major qPUF categories in terms of security assumptions, advantages, limitations, and practicality; and
3. Identify the main research challenges that must be addressed to make qPUFs a rigorous and useful hardware-security primitive.

The presenter works at the intersection of authentication, hardware security, and quantum cryptography, with a research focus on quantum-enhanced hardware roots of trust and quantum PUFs.

Requirements/Prerequisites:

Target audience: Researchers, practitioners, and graduate students in cryptographic hardware, embedded security, hardware authentication, roots of trust, and applied cryptography; also attendees interested in quantum cryptography and emerging hardware security assumptions.

Participants should bring their own laptops to take part in the hands-on portions of the tutorial. No specialised hardware or access to a quantum computer is required, as all experiments will be performed in simulation. Participants should have Python 3.10 or later installed on their laptops and be able to install the required Python packages. Detailed setup instructions, including the required software, Python packages, and tutorial materials, will be distributed in advance. Participants will be encouraged to complete the setup before attending the tutorial to minimise setup time during the session.

Time:

Sunday, October 11, 2026

Location:

TBA

Speaker:

• Azade Rezaeezade, Radboud University, NL

Abstract:

Electronic devices, ranging from simple smart cards to advanced hybrid vehicle systems, have become embedded in all aspects of our lives. Because these devices process sensitive information, manufacturers rely on cryptography to protect it. However, implementing cryptographic algorithms on embedded devices can itself introduce leakage through physical side channels such as power consumption and electromagnetic emissions. Therefore, rigorous side-channel security evaluation is essential to determine whether cryptographic implementations on embedded devices provide sufficient real-world protection. Deep learning has shown strong potential for exploiting side-channel leakage, but its use often comes with high costs due to extensive hyperparameter tuning and large data requirements. This tutorial introduces four techniques that help to make deep learning-based side-channel analysis (DL-SCA) more practical and cost-effective for security evaluation. These techniques (using regularization techniques, ensemble learning, multitask learning and customized deep learning elements) are cost-effective alternatives for intensive hyperparameter tuning and have been shown to be very effective.

Deep learning and artificial intelligence in general are receiving more and more attention these days for different purposes. Side-channel analysis is not an exception. Recently, there have been many papers and documents on the application of deep neural networks for side-channel evaluation. However, most works are more focused on introducing novel methods that improve the DL-SCA performance for a specific problem, while basic methods and techniques that are more common for improving deep learning efficiency in different domains are less studied and used. Considering this, the goal of this tutorial is to present the application of these methods, which are cost-effective and efficient.

This tutorial introduces deep learning-based side-channel analysis (DL-SCA), including its applications, the challenges of hyperparameter tuning across new measurement sets, and enhancement techniques that improve neural network generalization while reducing reliance on extensive tuning. It covers key methods such as regularization, ensemble learning, multitask learning, and customized neural network components, with practical examples showing how L1/L2 regularization, dropout, early stopping, ensemble attacks, multitask AES key-byte attacks, and the JumpReLU activation function can improve SCA performance. The tutorial concludes with a wrap-up and Q&A session.

Requirements/Prerequisites:

This tutoroal aims at researchers new to the field, graduate students, practitioners in SCA evaluation labs with basic knowledge of symmetric/asymmetric cryptography and side-channel analysis as well as familiarity with deep learning. Basic programming skills in Python are required.

Time:

Sunday, October 11, 2026

Location:

TBA

Speaker:

• Amin Abdulrahman, MPI-SP
• Matthias J. Kannwischer, ZeroRISC

Co-organizers:

• Hoang Nguyen Hien Pham, MPI-SP
• Kat Fox, ZeroRISC

Abstract:

The Pavona open-source silicon distribution makes production-quality, certification-ready secure hardware openly available and composable. It provides a modular library of tapeout-proven IP blocks and reference designs for building secure-by-default chips, building on prior efforts such as OpenTitan. Its cryptographic stack spans symmetric primitives such as AES and SHA-2/SHA-3, classical public-key cryptography, and post-quantum schemes (ML-KEM, ML-DSA, and SLH-DSA). Crucially, while Pavona is a commercial-grade implementation, it also serves as an ideal platform for research exploration: it is openly available, extensible, and has readily available getting-started guides and tooling that make it approachable. This dramatically lowers the barrier to experimenting with cryptographic hardware-software co-design, in which cryptographic routines and the accelerators they run on are developed together, leading to higher performance and easier to maintain implementations. Our tutorial focuses on Pavona's Asymmetric Cryptography Coprocessor (ACC), a programmable coprocessor capable of efficient big-number arithmetic for classical and SIMD processing for post-quantum schemes that ships with built-in countermeasures against physical attacks.

This tutorial will give participants hands-on experience with the complete co-design loop on Pavona's ACC. We begin with an overview of the full stack – from accelerator software, through the instruction-set architecture, down to the RTL – so that participants gain a mental model of how the pieces fit together. We will also give an overview of countermeasures against side-channel leakage and fault injection attacks and how the design is evaluated in practice. Participants will then (1) write and simulate accelerator software using its Python instruction-set simulator (ISS); (2) extend the ISS with a new custom instruction; and (3) implement that same instruction in SystemVerilog RTL and verify it in cycle-accurate Verilator simulation.

Requirements/Prerequisites:

Participants should bring their own laptops to take part in the hands-on portions of the tutorial. The tutorial environment runs on Ubuntu (22.04, 24.04, or 26.04), natively or via a virtual machine. Setup instructions and the necessary materials will be distributed in advance to minimize setup time during the session. No specialized hardware is required, as everything runs in simulation.